1. Technical Field
The embodiments herein generally relate to electrical circuits, and, more particularly, to sigma-delta loop filter circuits.
2. Description of the Related Art
A Sigma-Delta Analog-to-Digital Converter (ΣΔADC) typically includes a loop filter, a quantizer, and a feedback Digital-to-Analog Converter (DAC). Sigma-Delta Analog-to-Digital Converters may be continuous time or discrete time converters, the distinction between the two types being in the implementation of the loop filter. In a Continuous Time Sigma-Delta (CT-SD) ADC, the loop filter is built using components that don't need a clock to operate, such as (a) resistor, capacitors and opamps, (b) voltage-to-current converters, or (c) inductor and capacitors etc. The loop filter behavior can be characterized by its corresponding s-domain transfer function. The Discrete Time Sigma-Delta (DT-SD) ADC involves clocked switches and its loop filter characteristics are best described with its z-domain transfer function.
Anti-aliasing is a technique of minimizing the aliasing effects (distortion or artifact that results when a signal is sampled and reconstructed as an alias of the original signal) caused by components of the signal and noise with frequencies of half or more of a sampling rate. In discrete-time Sigma-Delta converters, an anti-aliasing filter is needed to filter out all unwanted signal above half of the clock frequency. As a contrary, the continuous Sigma-Delta ADC has an inherent anti-aliasing function built into the loop filter and it doesn't require a separate anti-aliasing filter in front of it which is very attractive to many applications.
Due to the sampling action of the clocked loop filters, discrete-time Sigma Delta ADC's building blocks such as opamps and reference has to be very fast to settle within one clock period so as not to introduce additional errors. This limits its maximum clock frequency and as a consequence its obtainable signal bandwidth. In contrast, continuous-time loop filters expand new application possibilities as it enables the use of a much faster system clock to increase signal bandwidth.
FIG. 1 is a typical ΣΔADC 100 having a loop filter 102, a quantizer 104, and a feedback DAC 106. The loop filter 102 receives input, IN, performs signal processing (e.g., removes unwanted signal components and/or enhances desired signal components), and sends its output signal Y to the quantizer 104. The loop filter 102 passes low-frequency signals and attenuates (reduces the amplitude of) signals with frequencies higher than a cutoff frequency. The loop filter 102 provides large gain within a signal band of interest. The loop filter 102 may be implemented using an integrator (not shown).
The quantizer 104 receives the output signal Y from the loop filter 102 as its input signal and quantizes the received input signal (e.g., converts the discrete signal into digital signal). The quantizer 104 divides a continuous range of values of a wave into a finite number of sub-ranges. Each sub-range of the wave may be represented by an assigned or quantized value. The digital signal obtained from the quantizer 104 is received by the feedback DAC 106, which then converts it into an analog signal that is fed to the loop filter 102 as an input signal. The integrator used to realize the loop filter 102 may be based either (i) on resistors, capacitors, and an op-amp, or (ii) on a voltage-to-current converter and capacitors.
FIG. 2A is a differential integrator circuit 200 based on a voltage-to-current converter (Gm) 202 and capacitors (CP and CN) 204. FIG. 2B is a conventional differential integrator circuit 210 based on capacitors (CP and CN) 204, an op-amp 206, and resistors (RINP and RINN) 208 illustrating the vulnerability of the circuit 210 to disturbance at the input of the op-amp 206. The resistors (RINP and RINN) 208 receive the inputs VINP and VINN and produce current according to the voltage across it and the current then get integrated on the capacitor Cp and Cn to produce the outputs VOUTP and VOUTN. According to the following equations: VOUTP−VOUTN=−(VINP−VINN)/sRC+(VOP−VON)(1+1/sRC), where R is the value of resistor RINP and RINN and C is the value of capacitor Cp and Cn.
So it is clear that non-linear signal content at the op-amp's input will produce distortion at the integrator output. Further, the output of the DAC 106 (of FIG. 1) (e.g., output from the quantizer 104) is an analog representation of digital signal so it is normally a step signal with sharp rising edges. If the step size is big, it will excite the first integrator 210 and causes the op-amp 206 in the first integrator 210 to undergo a transient process of slewing. During this process, the op-amp 206 exhibits strong non-linear behavior and non-linearity is translated into current and becomes integrated by the capacitor 204 to show up at the output.
This leads to distortion at the integrator output. This is a major bottleneck of the conventional differential integrator circuit 210 when it comes to signal to distortion. Thus, the conventional differential integrator circuit 210 is vulnerable to disturbance at the input of the op-amp 206. In addition to that, the anti-aliasing performance of the conventional differential integrator circuit 210 is degraded as the finite op-amp gain causes the integrator 210 to deviate from its ideal 1/s frequency response.
In a ΣΔADC with an order higher than 2 (e.g., third order configuration), the ADC may go unstable when the input exceeds certain maximum range. This affects system reliability. Therefore, in order to have a stable ADC, typically the loop filter may have to be reset or to limit the input signal within a certain range using an additional circuit element (e.g., an automatically controlled gain loop) to ensure that the input signal range is never higher than the stability threshold.
For low noise Sigma Delta ADC, there is a very tight demand for a previous stage's driving capability. For example, for a 1-volt peak-to-peak differential input signal, a 86 dB dynamic range within a 4 MHz band dictates a 4,700 ohm input resistance, if implemented using the traditional method, whereby the preceding stage typically has to provide 0.1 mA when driving the ADC with a full 1-volt signal swing. This is normally too much current load for the previous stage without a buffer. Thus the conventional approach for low noise ADC normally also implies a buffer in between the previous stage driving into the ADC. So a continuous time Sigma Delta ADC with capacitive input impedance, inherent stability and immunity to opamp's virtual ground bounce is highly desired.